Question

use an edge triggered JK flip-flop to design and construct a divide-by-10 synchronous counter.

Answer 1

the logic equations are\[J _{D}=ABC\]\[K_{D}=A\]
\[J_{C}=AB\]\[K_{C}=AB\]
\[J _{B}=AD'\]\[K_{B}=A\]
\[J_{A}=1\]\[K_{A}=1\]

Answer 2

need help in the logic circuit diagram using 7476 dual D flip flop IC