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OpenStudy (anonymous):
Suppose that in 1000 memory references there are 40 misses in the first level cache . 20 misses of them are missed in the second level cache too. Assume the miss penalty from the L2 cache to memory is 100 clock cycles, the access time of L1 is 1 clock cycle, and there are on average 1.5 memory references per instruction. What is the average memory access time and how many misses will be there per 1000 instructions?
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