The drain of Q1 is still high and the gate of Q2 is at VOL. A STORE pulse comes in and turns on Q3. How long must the STORE pulse be on, in picoseconds, to charge the gate capacitance of Q2 to VOH?
incorrect
Note: In fact, the SR model is not very accurate for Q3 in this circuit because Q3 is in saturation, but use the SR model anyway, for simplicity.

Now, suppose DIN is high, the drain of Q1 is low, and the gate of Q2 is at VOH. A STORE pulse comes in and turns on Q3. How long must the STORE pulse be on, in picoseconds, to discharge the gate capacitance of Q2 to VIL?

Question

The drain of Q1 is still high and the gate of Q2 is at VOL. A STORE pulse comes in and turns on Q3. How long must the STORE pulse be on, in picoseconds, to charge the gate capacitance of Q2 to VOH?
incorrect
Note: In fact, the SR model is not very accurate for Q3 in this circuit because Q3 is in saturation, but use the SR model anyway, for simplicity.

Now, suppose DIN is high, the drain of Q1 is low, and the gate of Q2 is at VOH. A STORE pulse comes in and turns on Q3. How long must the STORE pulse be on, in picoseconds, to discharge the gate capacitance of Q2 to VIL?