According to Computer Logic Gates, the Full Adder Circuits consists of two Half Adders and one OR Gate. The use of the OR Gate in the Full Adder Circuit is to add the output carry of the 1st Half Adder and the 2nd Half Adder. As per the Truth Table of the OR Gate and XOR Gate, the first three rows are (0+0=0, 0+1=1, 1+0=1) common to OR Gate and XOR Gate. The last row is entirely different from each other and the last row is not acted upon in Full Adder circuit. Hence why should not use another one XOR Gate in the the place of OR Gate in Full Adder circuit in order to add the output Carry of

Question

According to Computer Logic Gates, the Full Adder Circuits consists of two Half Adders and one OR Gate.  The use of the OR Gate in the Full Adder Circuit is to add the output carry of the 1st Half Adder and the 2nd Half Adder. As per the Truth Table of the OR Gate and XOR Gate, the first three rows are (0+0=0, 0+1=1, 1+0=1) common to OR Gate and XOR Gate. The last row is entirely different from each other and the last row is not acted upon in Full Adder circuit.  Hence why should not use another one XOR Gate in the the place of OR Gate in Full Adder circuit in order to add the output Carry of

anonymous · Answer

Correction to Question: 
That is the last row of the Truth Table (1+1=1) of the OR Gate is not acted upon in the Full Adder Circuit.  Hence why should not use another one XOR Gate in the place of OR Gate in order to add the output Carry of the two Half Adders?

turingtest · Answer

I think perhaps this belongs in the computer science section