Question

I have a confusion related to Synchronized flip-flop.

Answer 1

After studying transparent flip flop, we moved to clocked flip flop saying that it has more advantages: e.g
Irrespective of the input, output will remain in its last stage and can change only a when clock pulse arrive . If the input fluctuates due to some error or other external interference, there won't be any effect on the output if the clock pulse is absent. And hence once we apply the input, latch it, we can save this data bits for a long time. To make it more effective edge-triggered flip-flop is constructed.
My question is: in a computer, clocks are running with a fixed frequency, means clock pulse is applied continuously after a very short interval (isn't it?). Then now if D input changes due to some reason, output will also change with the arrival of next clock pulse. So how is it really different from unclocked or transparent flip flop.

Answer 2

I'll just comment about clocking to say this: there's the ideal world, where all the signals have nice clean edges, and the clocks are perfectly syncronized, and there's the real world, where everything is built out of analog devices, signals do not have those nice sharp edges you see in the diagrams, clock signals take time to propagate, noise issues, etc. There are plenty of people who can hook up flip-flops successfully when the clock runs at 50 KHz, but the ranks of the people who can figure out why the circuit doesn't work properly once every few hours when the clock runs at MHz-GHz rates are very thin, and when you meet one of those people, attempt to learn everything you can from them!

Answer 3

Suppose you have a lot of complicated combinatorial logic that is pipelined with registers (a clocked flip flop). You'll have something like this:


The first block of combinatorial logic reads the first register, does something with that data and presents the result to the next register. At the same time, the second combinatorial logic block reads the value from the second register, does something and presents its value to the third register.

Now suppose you have a transparaent FF (Flip Flop). The first block changes that data very fast and presents its value. The value will pass through the FF and the second block (which was working with the original value) now continues it's calculations with that new value. That can be a problem and lead to glitches.

In the same situation, but with clocked FFs, there'll be no glitches. Block one determines the new value very fast, but it won't be stored in the FF as long as the FF is not triggered by the clock. This will keep the original value in the second register and the second block of logic won't use the new data until it's put into the register.

I hope it's a bit clearer for you now. If you, I'll try to explain better.