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MIT 6.002 Circuits and Electronics, Spring 2007 6 Online
OpenStudy (anonymous):

Hi, I need to design a circuit which gives positive half cycle of sine wave when logic 1 is given as input and negative cycle of sine wave when logic 0 is input. Please let me know how to design the same using cadence.

OpenStudy (anonymous):

Do you want the negative cycle of the sine wave to be a negative voltage? Or do you want the circuit to always output a positive voltage?

OpenStudy (anonymous):

I want -ve cycle for -ve voltage.

OpenStudy (kenljw):

Try using two SCR (silicon controlled rectifiers)

OpenStudy (arnavguddu):

use 2 SCR.... SCR 1 will be target of logic 1....forward biased in sine positive... SCR 2 will be target of INVERT logic 1 .... reverse biased in sine negative....

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