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MIT 6.002 Circuits and Electronics, Spring 2007
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show that positive logic nand gate is negative logic nor gate
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Not (A and B) = Not (A) or Not (B) by use of De Morgan theorem
let A & B be two inputs to a NAND gate and Y be output A B Y L L H L H H H L H L L H In a negative logic circuit L(low voltage level) represents logic '1' and H(high voltage level) represents logic '0' and conversely for positive logic circuits. So for positive logic you put L=0 and H=1 you will get the table for positive logic NAND gate .If now you put H=0 and L=1,you will get a table for NOR gate and obviously it is in negative logic.
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