Need some help with VERILOG

keep getting an error after compiling:
module L2P4(a,b,c,d,f1,f2);
input a,b,c,d;
output f1, f2;

wire a,b,c,d,f1,f2;
wire and1out,and2out,and3out,and4out,and5out,notaout,notbout,notcout,notdout;

not nota(notaout,a), notb(notbout,b), notc(notcout,c), notd(notdout,d);

and and1(and1out,a,notbout,c), and2(and2out,notcout,d), and3(and3out,notaout,notbout), and4(and4out, c,notdout);

or fone(f1, and1out,and2out),
ftwo(f2,and3out,and2out,and4out,and5out);
endmodule

The above is the code

Question

Need some help with VERILOG

keep getting an error after compiling:
module L2P4(a,b,c,d,f1,f2);
	input a,b,c,d;
	output f1, f2;
	
	wire a,b,c,d,f1,f2;
	wire and1out,and2out,and3out,and4out,and5out,notaout,notbout,notcout,notdout;
	
	not nota(notaout,a), notb(notbout,b), notc(notcout,c), notd(notdout,d);
	
	and and1(and1out,a,notbout,c), and2(and2out,notcout,d), and3(and3out,notaout,notbout), and4(and4out, c,notdout);
	
	or fone(f1, and1out,and2out),
		ftwo(f2,and3out,and2out,and4out,and5out);
endmodule

The above is the code

anonymous · Answer

The error that comes out making me not able to assign pins:

Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Critical Warning (169085): No exact pin location assignment(s) for 6 pins of 6 total pins. For the list of the pins please refer to the Input Pins, Output Pins, and Bidir Pins tables in the Fitter report and look for the user pins whose location is assigned by Fitter.