VERILOG XOR GATE

Got a simple XOR gate using NAND

For some reason when testing the code inputs (1,1) gives an output = 1

This is not correct.
Any reason what I'm doing wrong?

module L2P2(x,y,f);
input x,y;
output f;

wire x,y,f;

wire xnandyout, xnandout, ynandout;

nand xnandy(xnandyout, x,y);
nand xnand(xnandout, x, xnandyout);
nand ynand(ynandout, y, xnandout);
nand fout(f,xnandout,ynandout);
endmodule

Question

VERILOG XOR GATE

Got a simple XOR gate using NAND

For some reason when testing the code inputs (1,1) gives an output = 1 

This is not correct.
Any reason what I'm doing wrong?


module L2P2(x,y,f);
	input x,y;
	output f;
	
	wire x,y,f;
	
	wire xnandyout, xnandout, ynandout;
	
	nand xnandy(xnandyout, x,y);
	nand xnand(xnandout, x, xnandyout);
	nand ynand(ynandout, y, xnandout);
	nand fout(f,xnandout,ynandout);
endmodule