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MIT 6.002 Circuits and Electronics, Spring 2007 7 Online
OpenStudy (anonymous):

why are asynchronous sequential cicuits unstable?

ganeshie8 (ganeshie8):

clocks are not related in async ckts, so the data is not guaranteed to not change when the active clock edge transits, and data gets sampled by flop. so we need to synchronize the async interface using fifo or by some other means

OpenStudy (anonymous):

And even no trigger is applied here.

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