Question

Use a 3-to-8 decoder, NAND gates, and edge-triggered D flip-flops to design a 4-bit shift register module that has the following function table:

Answer 1

S2 S1 S0 Mode
0 0 0 shift right (all 4 bits)
0 0 1 Shift left (all 4 bits)
0 1 0 Synchronous common clear
0 1 1 Synchronous parallel load
1 0 0 Synchronous preset MSB to 1 and clear other bits
1 0 1 Synchronous data hold
1 1 0 Ring counter (Q output of LSB is fed back as serial input to the MSB)
1 1 1 Twisted-ring counter (Qnot output of LSB is fed back as serial input to the MSB)