Question

Q4 n Q5 .Please help.

Answer 1

Q1

In this problem, we look at the design of an inverter. For the entirety of this problem VS=7.0V, and all transistors are modeled with the SR model with RON=120Ω. We design the inverter shown in Figure 1.


Figure 1
The static discipine of the inverter is VIL=2V, VOL=1V, VIH=5V, and VOH=6V. What is the minimum resistance (in Ohms) that R can be to meet this static discipline?

unanswered

We now cascade two of these inverters shown in Figure 2. Assume that R=3kΩ. We want to ananlyze the speed of our inverter, so we model the parasitic capacitance at node B as the gate-to-source capacitance of the the second gate, CGS=0.3pF.


Figure 2
First we consider the case where the voltage at node B is rising. What is the time (in nanoseconds) after the falling edge at node A, that it takes for the signal at node B to rise from 0V to VOH=6V?
unanswered

Now we consider the case where the voltage at node B is falling. After the rising edge at node A, what is the Thevenin equivalent resistance (in Ohms) as seen by the gate-to-source capacitance, CGS?

unanswered
What is the time constant, τf (in picoseconds), for this falling transient voltage?
unanswered
What is the time (in picoseconds) that it takes for the signal at node B to fall from 7.0V to the value of VOL=1V?

Answer 2

@Kuba222 wrong....

Answer 3

i did but didnt find

Answer 4

sorry wrong ...last attempt@kuba222