Question

how to implement cmos logic

Answer 1

Can you be more specific?

I'm not sure this is the best place to get an answer to your question but having said that CMOS logic levels are different from TTL logic levels for example. CMOS input logic level HIGH state is +5 +/- 1.5 V and LOW state is 0.0 +/- 1.5 V. The output levels are suppose to be typically +5V +/-0.1V abd 0.0 +/-0.1V.

TTL levels at input are HIGH > +2.0 V and LOW < +0.8V. while worst case output levels for TTL are HIGH +2.4 V and LOW +0.4 V.

So you must watch you signal levels more carefully with CMOS logic. CMOS is less noise sensitive.