Question

SR latches

Answer 1

I am having trouble drawing the time diagram. I know that we introduce the clock signal to avoid oscillations when S and R both equal 1. And that C changes to 1 only when S and R are stable.

Answer 2

@sidsiddhartha

Answer 3

@Ashleyisakitty @zepdrix

Answer 4

Generally transition from input to output on a clocked gate either on leading edge or trailing edge of the clock signal. Then there's a transition time from edge to output which actually place limits on clock frequency. Generally for discrete IC gates the data is available as they may have different delays, of course the less delays are more expensive.

Answer 5

Still working this, or did you want to close it?