Question

“Why does pipelining improve performance?”

Answer 1

Problem:
“Why does pipelining improve performance?”

Solution:
“In an unpipelined processor, each instruction is executed completely before execution of the next instruction begins. In a pipelined processor, instruction execution is divided into stages, and execution of the next instruction starts as soon as the current instruction has completed the first stage. This increases the rate at which instructions can be excuted, improving performance.

Another way to describe this is thatr pipelining divides the processor's datapath into stages that are separated by pipeline latches. In an unpipelined processor, an instruction must be able to get all the way through the datapath withi a single clock cycle. In a piepelined processor, an instruction must only be able to get through one stage of the pipeline in each cycle, allowing the clock cycle to be much shoter than in an unpipelined processor. Since a pipelined processor can still start executing one instruction during each clock cycle increases the rate at which instructions can be executed, improving performance.”

My question is:
Is “In a piepelined processor, an instruction must only be able to get through one stage of the pipeline in each cycle, allowing the clock cycle to be much shoter than in an unpilelined processor.” supposed to be “In a piepelined processor, an instruction must only be able to get through one stage of the pipeline in each cycle, allowing the clock cycle TIME to be much shoter than in an unpipelined processor.”?

Any input would be greatly appreciated! :)

Answer 2

thats right interpretation. in a pipelined processor clock cycle time reduces by a factor of num of pipeline stages (ideal, without considering latch delays)

Answer 3

Thanks for you answer but, it seems like I can interpret that in two ways.: Which interpretation is right? Mine or that of the author of the book I quoted?

Answer 4

"...allowing the clock cycle to be much shoter" means, allowing hte clock cycle period to be much shorter. period is implicit here.

clock period is measured in time units. can you tell wats the second interpretation you see here...

Answer 5

The second interpretation I see is frequency, which is the inverse to the time period.

Answer 6

okay. in general short clock cylce implies higher frequency. short clock cycle doesnt imply lower frequency

Answer 7

So, is that a YES to the initial question I had, which is:

Is

“In a pipelined processor, an instruction must only be able to get through one stage of the pipeline in each cycle, allowing the clock cycle to be much shorter than in an unpipelined processor.”

supposed to be

“In a pipelined processor, an instruction must only be able to get through one stage of the pipeline in each cycle, allowing the clock cycle TIME to be much shorter than in an unpipelined processor.”

?

(Notice the emphasized, capitalized part of the last quote.)

(I'm looking for a direct confirmation, assuming I am right and, also, sorry if you already said this and I didn't realize it; I'm tired today and was also tired yesterday.)

Answer 8

yes you have it right :)

...allowing the clock cycle TIME to be much shorter than in an unpipelined processor.

is the only correct interpretation here.

lot of implicit meanings authors assume in all books... these things we understand with experience. appreciate that you took time to clarify...

Answer 9

Thanks a lot for confirming. :)