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MIT 6.002 Circuits and Electronics, Spring 2007 7 Online
OpenStudy (anonymous):

can any 1 xplain me why it's got to be like this?

OpenStudy (anonymous):

OpenStudy (nick67):

@A.Avinash_Goutham Hi Avinash, dashed regions are allowed level in order to have a good matching between gates. These conditions ensure that: VOH > VIH , when the first gate output is high (1), it's level is always higher than the minimum accepted input level for the second gate to be high (1). VOL < VIL , when the first gate output is low (0), it's level is always lower than the maximum accepted input level for the second gate to be low (0). Hope have been useful.

OpenStudy (anonymous):

sir, how does that benefit the circuit? i thot it s related to noise

OpenStudy (nick67):

you're right if signals are affected by noise, it may happen that levels go below or above permitted level, entering in middle zones, with unpredictable results on gate output

OpenStudy (anonymous):

so in some cases out put turns out be x instead of a 1/0

OpenStudy (nick67):

you have to check IC datasheet to know that; in some cases they put some sort of hysteresis on gate behavior, so that if the input doesn't change enough the output remain the same

OpenStudy (anonymous):

i think i get it ............thank you sir :)

OpenStudy (nick67):

you're welcome, have a nice Sunday

OpenStudy (anonymous):

:D my day's almost over have a nice sunday sir:))

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