Question

Problem: http://screencast.com/t/ukTWbOdD6x
Solution: http://screencast.com/t/ORTe02rC3A1

My Question: Why Q1 and Q2 doesn't move at all?

Answer 1

@ganeshie8

Answer 2

which clock cycle you talking about

Answer 3

here reset is active LOW - if reset is active when the clock active edge ticks, the flop output becomes 0.

Answer 4

Can you tell me where is the reset?

Answer 5

well ,


it's a counter and it starts with 1000


Q3 Q2 Q1 Q0

1 0 0 0

next , it will be

1 0 0 1


then , clear signal was applied

0 0 0 0

next, we count over again


0 0 0 1

Answer 6

But why this: http://screencast.com/t/jbajrrmG

Answer 7

No change at all

Answer 8

look at my work above, did Q1 and Q2 change at all?

Answer 9

Is that really the only logic behind this?

Answer 10

?

Answer 11

I cant believe it was so simple, I guess that's the logic

Answer 12

there ?

Answer 13

// Can you tell me where is the reset?

CLR' is the active low reset

Answer 14

I really cant spot it gane :(

Answer 15

Thats the clock, what does it have to do with reset?

Answer 16

CLK is the clock.
CLR' is the clear/reset signal. you need to sleep a bit i guess u working too much last few days

Answer 17

Yes CLK is the clock, but what does the clock have to do with the reset? I really couldn't sleep today bro, thanks for your care !

Answer 18

whats your question exactly

Answer 19

My main question is this http://screencast.com/t/0i1Li8rB why does it stay untouched?

Answer 20

you took that snap from the middle section of state table.
look at the solution snap to see the fuller context. try to follow my explanation. il walk u step by step

Answer 21

ok your explanation was because it is reset, that's why I asked you about the reset because I can't understand it I thing

Answer 22

im going to explain it step by step. have patience :)

Answer 23

ooh ok ;p

Answer 24

attached solution snap, do you understand how Q0, Q1, Q2, Q3 changed in first clock cycle ?

Answer 25

its because the problem says so

Answer 26

problem says what ? problem only gives us the initial state of 1000, CLR and CLK signals.
it doesnt tell us about how Q0, Q1, Q2, Q3 change in each cycle. we need to figure that out ok

Answer 27

oooh sorry I misunderstood! For this I only understand Q0 the rest go ubnormally to my mind

Answer 28

it happens to me a lot lol...

so this is the thing we are trying to work out :- to figure out the values of Q0, Q1, Q2, Q3 in each cycle.

Answer 29

First cycle :-
1. CLR is not active, so counter functions normally, increments its previous value 1000 to 1001

Answer 30

Second cycle :-
2. CLR is not active, so counter functions normally, increments its previous value 1001 to 0000 (remember its a BCD counter)

Answer 31

Third cycle :-
3. CLR is active, so counter resets to 0000

Answer 32

Fourth cycle :-
4. CLR is active, so counter resets to 0000

Answer 33

Fifth cycle :-
5. CLR is still active, so counter resets to 0000

Answer 34

Sixth cycle :-
6. CLR is not active, so counter increments its previous value 0000 to 0001

Answer 35

does it make sense

Answer 36

in short :- each cycle, the counter checks for CLR signal. if CLR is active, counter resets to 0000. if CLR is not active, counter increments its previous value.

Answer 37

Did you do this vertically or horizontial with only one Q/line?

Answer 38

any sequential stuff we do vertical always, becoz time is in horizontal. we want to work out all output values at a particular instance of time.

Answer 39

I see

Answer 40

you can think of each cycle of clock here, as each hour of a day..

Answer 41

each hour, we are trying to see what the output values are.

Answer 42

the counter increments its value each hour, if the CLR signal is not active. simple rule huh ?

Answer 43

Yes I got it

Answer 44

good... take ur time.. takes time to settle in head... ping if u get uncertain again