Question

m120 errarta

Answer 1

\(\huge\color{blue}{Welcome~To~OpenStudy!}\)
What is your specific question? @lpstring2012

Answer 2

It sounds confusing to me.

Answer 3

External clock synchronization on M120 routers is supported but not currently documented in the M120 Hardware Guide. External clock synchronization enables you to configure an interface that synchronizes the router’s internal Stratum 3 clock to an external source, and then synchronize the chassis interface clock to that source. You can configure the feature for external primary and secondary interfaces that use Building Integrated Timing System (BITS) or SDH Equipment Timing Source (SETS) timing sources, or an equivalent quality timing source. To configure, include the synchronization statement at the [edit chassis] hierarchy level. To view information about the external source used for chassis synchronization, issue the show chassis synchronization command. To change the external clock source, issue the request chassis synchronization switch command. To change the external clock source, issue the request chassis synchronization switch command. Refer to the System Basics, and System Basics Command Reference for configuration information.

Answer 4

Can you please cite your sources? @cebroski

Answer 5

http://www.juniper.net/documentation/en_US/release-independent/junos/topics/reference/general/m120-errata.html

Answer 6

The M120 Multiservice Edge router is a complete routing system that provides SONET/SDH, ATM, Ethernet, and channelized interfaces for large networks and network applications, such as those supported by Internet service providers (ISPs) and large enterprise customers. Application-specific integrated circuits (ASICs), a definitive part of the router design, enable the router to forward data at the high speeds demanded by current network media.
The router provides multiple redundancy options and chassis configurations, enhanced ASIC features, and chassis and Packet Forwarding Engine (PFE) scaling. PFE routing functionality is performed by Forwarding Engine Boards (FEBs) which separate routing ASICs from Flexible PIC Concentrators (FPCs) to provide high availability and redundancy of the forwarding engine. The router utilizes the I-chip ASIC, which supports up to 32,000 logical interfaces depending on your configuration. The base chassis provides 120 gigabits per second (Gbps) of midplane bandwidth between the interfaces and FEBs, and 144 Gbps, half duplex, of fabric bandwidth between the FEBs.
The router is a quarter-rack chassis that supports up to six FPCs. Four slots accept FPCs of Types 1, 2, and 3 and two slots accept Compact FPCs (CFPCs). Each FPC can be configured with a variety of network media types, altogether providing up to 130 physical interface ports per system. The CFPC slots are identical to the Type 1, 2, and 3 FPC slots, but feature a smaller form factor to provide higher density 10-Gigabit interfaces. The router height of 20.75 in. (52.71 cm) enables stacked installation of four routers in a single floor-to-ceiling rack, for increased port density per unit of floor space. In a standalone configuration, the router's maximum aggregate throughput is 60 Gbps, full duplex.
The router architecture separates control operations from packet forwarding operations, which helps to eliminate processing and traffic bottlenecks. Control operations in the router are performed by the Routing Engine, which runs Junos OS to handle routing protocols, traffic engineering, policy, policing, monitoring, and configuration management. Forwarding operations in the router are performed by the Packet Forwarding Engine (PFE), which includes ASICs, designed by Juniper Networks contained on the FEBs. The redundant FEBs provide route lookup and forwarding functions from the PICs and CFPCs with fast switchover times and higher bandwidth PFEs provide support for larger numbers of PICs.

Source: http://trapezenetworks.com/techpubs/en_US/release-independent/junos/information-products/pathway-pages/m-series/m120/index.html

Answer 7

I wonder what the probability is that lpstring2012 has a math question about the m120 errarta?